Selecting Pull-Up and Pull-Down Resistors

Selecting Pull-Up and Pull-Down Resistors

Pull-up and pull-down resistors define a known logic state on a signal line when nothing is actively driving it.¹

Choosing the wrong value causes real problems: too low a resistance wastes current and may overload the driver; too high a resistance allows the signal edge to rise slowly, causing timing errors on fast I²C buses or missed button presses in noisy environments. Understanding the trade-off between power consumption and edge speed guides every pull-up selection.

Why pull-ups are needed and the selection formula

Inside a microcontroller, GPIO inputs have extremely high impedance (effectively open circuits). Without a pull-up, a momentary switch floats when open, susceptible to induced voltage from nearby traces. A pull-up connects the line to VCC through a resistor, holding it high until actively pulled low. The resistor value sets the current: I = VCC / R when the line is pulled to ground. For R = 10kΩ and VCC = 3.3V: I = 0.33 mA.

For I²C, the specification constrains the pull-up: R must satisfy both the minimum VOH requirement and the maximum rise-time requirement. Rise-time limit: R × Cbus <= 1000 ns for 100 kHz standard mode. When a bus with 200 pF total capacitance uses a 4.7kΩ pull-up, the rise time constant is 4.7kΩ x 200 pF = 940 ns, which falls within the 1 µs limit, but adding a fourth device with 50 pF input capacitance pushes the total to 250 pF and the rise time to 1.175 µs, barely exceeding the specification and causing intermittent communication failures that are difficult to reproduce.

Balancing current, edge speed, and bus capacitance

A stronger pull-up improves rise time but wastes current when the line is low. A weaker pull-up saves power but can fail on long or fast buses, so size an I²C pull-up from bus capacitance and speed class rather than guessing. The bus capacitance is the sum of all pin capacitances, trace capacitances, and connector capacitances on the line, and it directly determines how fast the pull-up resistor can charge the bus to a valid logic high during each clock cycle.¹ When you add a third I²C device to an existing bus and the rise time margin disappears, the total bus capacitance has increased beyond what the existing pull-up value can handle, and reducing the pull-up resistance restores reliable communication.

Step-by-step selection process

First, determine the bus protocol. For I²C: calculate R from the bus capacitance. For simple GPIO or button inputs: start with 10kΩ. Second, check the driver's sink current IOL, which is the maximum current it can sink while staying within the VOL specification. If the pull-up is too strong, the driver cannot pull the line low enough to register as a valid logic low, and every read returns corrupted data.

Selecting the nearest standard value

Third, ensure R >= (VCC - VOL) / IOL to avoid exceeding the driver's sink capability. Fourth, for I²C, calculate R_max = 1000 ns / Cbus. A 400 pF bus gives R_max = 1000 ns / 400 pF = 2.5kΩ. Fifth, select the nearest standard E-series value within the constraints: 4.7kΩ for 100 kHz I²C with typical bus under 200 pF, 2.2kΩ for 400 kHz or loaded buses. When the calculated ideal value falls between two standard parts, always choose the lower resistance option because a slightly stronger pull-up costs a fraction of a milliamp extra but guarantees reliable communication even as bus capacitance increases from added devices or longer cables.

For a battery-powered I²C sensor node that spends 99% of its time in deep sleep, the quiescent current through the pull-up resistors dominates the standby budget, and choosing 10kΩ instead of 2.2kΩ reduces the bus idle current from 1.5 mA to 0.33 mA at 3.3V, extending the battery life from weeks to months. When the I²C bus operates at 1.8V instead of 3.3V, the same pull-up resistance draws less current, but the reduced voltage margin means the pull-up value must be lowered to maintain acceptable rise times, and recalculating from bus capacitance at the new voltage is essential for reliable communication.

For a design that must operate at both 3.3V and 1.8V, selecting a pull-up value that satisfies the rise-time constraint at the lower voltage ensures reliable communication at both levels, though the higher voltage operation will draw more quiescent current than strictly necessary. When the I²C bus uses 4.7kΩ pull-ups at 3.3V and the bus capacitance is 150 pF, the rise time is 4.7kΩ x 150 pF x 2.2 = 1.55 µs, which exceeds the 1 µs standard-mode limit; reducing the pull-up to 2.2kΩ brings the rise time to 726 ns, well within spec, and the 1.5 mA idle current at 3.3V is acceptable for mains-powered designs.

For a battery-powered sensor node that wakes once per hour to read a sensor and transmit data, the pull-up current during the brief active period is negligible, but if the bus remains powered between samples, the continuous current through the pull-up resistors dominates the standby budget and selecting the highest acceptable resistance extends battery life proportionally.

When the bus uses 10kΩ pull-ups at 3.3V, each line draws 0.33 mA when pulled low, and with both SDA and SCL lines held low by a busy device, the total pull-up current is 0.66 mA, which is significant for a system with a 5 mA standby budget and should be factored into the overall power calculation.

Common mistakes and practical tips

Using 1kΩ pull-ups on I²C lines wastes 3.3 mA per line when the bus is idle, adding 6.6 mA to every device attached to the bus, which is significant for battery-powered nodes. Conversely, using 100kΩ on a 400 kHz I²C bus produces rise times of 40 µs (100kΩ x 400 pF), far exceeding the 300 ns maximum, guaranteeing communication failure.

Avoiding parallel pull-ups on shared buses

Multiple pull-up resistors on the same I²C bus from different modules stack in parallel, lowering effective resistance below individual values. Check total bus pull-up strength when connecting multiple I²C peripherals. For button inputs, debouncing time constants are set by R x C where C is the filter capacitor; a 10kΩ resistor with 100 nF gives a 1 ms filter. When a development board has onboard 4.7kΩ pull-ups and a sensor module with its own 4.7kΩ pull-ups is stacked on top, the effective 2.35kΩ resistance draws 1.4 mA per line at 3.3V, which may exceed the total GPIO sink budget and cause signal integrity issues that manifest as intermittent communication errors.

When two I²C modules each carry their own 4.7kΩ pull-ups, the effective bus resistance drops to 2.35kΩ, which draws twice the intended current and may exceed the GPIO sink capability of the weakest device on the bus. The resulting current surge when the bus is pulled low can force the weakest driver outside its guaranteed VOL range, so that a logic low is misread as an intermediate voltage and random bytes appear on the bus.

When sensor modules with onboard pull-ups are stacked on a development board, the combined parallel resistance can drop below the intended design value, causing excess current draw and potential communication failures that are difficult to diagnose without measuring the effective bus resistance with a multimeter. For a development board with three I²C sensor modules each carrying 4.7kΩ pull-ups, the effective bus resistance is 1.57kΩ, which draws 2.1 mA per line at 3.3V and may exceed the total GPIO sink budget of the microcontroller, causing signal integrity issues that manifest as intermittent communication errors that are nearly impossible to debug without systematically removing modules to isolate the cause.

Internal microcontroller pull-ups vs external resistors

Most microcontrollers include weak internal pull-up resistors on GPIO pins, typically 20kΩ to 50kΩ (RP2040: 50kΩ nominal; AVR ATmega: 20–50kΩ; STM32: 40kΩ typical).² These are convenient for simple button inputs but are too high-impedance for I²C buses and too variable in absolute value to use for timing-critical applications. The wide manufacturing spread of internal pull-ups means that two supposedly identical microcontroller boards could have pull-up values differing by 2x, which makes them unsuitable for any application where the exact resistance affects circuit behavior.

External resistors should replace internal pull-ups when: the line connects to multiple devices on an I²C bus where bus capacitance makes 40kΩ too slow for reliable signal edges; the pull-up voltage differs from the MCU supply voltage (level-shifting scenario); the line requires a tightly defined resistance for impedance-matching; or the design needs consistent pull-up behavior across a production run where the internal resistor spread would cause timing failures on a fraction of units.

For a standalone button input where exact timing is not critical, the internal pull-up is adequate and saves a component. For I²C, always use external resistors calculated from bus capacitance and speed class. CapyToolkit's pull-up selection guide helps you decide when the internal pull-up is sufficient and when an external resistor is required for reliable bus operation. When a design uses both internal and external pull-ups on the same I²C bus, the internal pull-up adds to the external resistance in parallel, lowering the effective pull-up value below the intended design point, and the internal pull-up should be disabled in firmware before enabling the external resistors.

For a typical AVR microcontroller with a 40 kΩ internal pull-up and a 4.7 kΩ external pull-up, the combined parallel resistance is 4.2 kΩ instead of the intended 4.7 kΩ, a 10% reduction that increases the bus current and may affect the rise-time margin, which is why the internal pull-up must be explicitly disabled when external resistors are present.

Pull-down resistors for MOSFET gate protection

N-channel MOSFETs require the gate at 0V when off to prevent phantom switching from stray capacitive coupling or gate leakage current. A pull-down resistor between gate and source holds the gate firmly low when the driver is not actively asserting a high level. When the gate driver is disconnected during programming or debugging, the pull-down resistor ensures the MOSFET remains off rather than floating to an undefined voltage that could cause unintended conduction and potentially damage the load or the power supply.

Values of 10kΩ to 100kΩ are typical: 10kΩ discharges the gate capacitance quickly while drawing only 0.5 mA from a 5V driver during the on state; 100kΩ reduces on-state gate current to 50 µA but discharges gate capacitance more slowly.³ For relay-driving transistors where fast turn-off is not needed, 100kΩ is common. For power-stage MOSFETs switching above 10 kHz, 10kΩ is the conventional starting point to prevent ringing and noise-triggered switching between drive pulses.

When a MOSFET gate pull-down resistor is omitted from a power-stage design, the floating gate can pick up enough noise from nearby switching traces to partially turn on the device during the off state, causing shoot-through current that heats both the MOSFET and the driver IC and can lead to catastrophic failure in high-current bridge configurations.

When to use this

Use this guide for any open-drain or open-collector bus (I²C, SMBus, 1-Wire, UART with external pull-up), any momentary switch or button input, and any GPIO input that needs a defined idle state. Recalculate whenever bus length changes significantly or you add more devices to an existing I²C bus.

Examples

Bus capacitance: 200 pF. Rise time limit: 1000 ns (100 kHz standard mode).
R_max = 1000 ns / 200 pF = 5kΩ. Chosen: 4.7kΩ.

Rise time: 4.7kΩ × 200 pF = 0.94 µs, which falls within the 1 µs limit. Current at 3.3V: 0.7 mA per line.

10kΩ pull-up, 100 nF debounce capacitor. RC = 1 ms. Button connected between input pin and ground.

Signal floats high at 3.3V when open. Button press pulls to 0V with 1 ms RC debounce. 0.33 mA while pressed.