PCB Trace Current Capacity and Ohm's Law

PCB Trace Current Capacity and Ohm's Law

A PCB trace carrying current behaves as a resistor determined by its width, thickness, and length. Copper's resistivity converts some of the electrical energy into heat as current flows, and the resulting temperature rise in the trace determines whether the FR4 substrate and solder mask survive long-term.¹ Standard 1-ounce (35 µm) copper has a sheet resistance of approximately 0.5 mΩ per square, meaning a trace one square wide and one square long has 0.5 mΩ of resistance regardless of its absolute size.² IPC-2221, the industry standard for PCB design, provides trace width tables that set the minimum width for a given current and allowable temperature rise, covering both external and internal copper layers at different weights.

Calculating trace resistance and temperature rise

Trace resistance follows R = ρ × L / (W × T), where ρ is the resistivity of copper (1.72 × 10⁻⁸ Ω·m), L is trace length, W is trace width, and T is copper thickness.³ For 1-ounce copper (T = 35 µm), a 1 mm wide, 50 mm long trace has R = 1.72e-8 × 0.050 / (0.001 × 0.000035) = 24.6 mΩ. At 1 A, the power dissipated is 1² × 0.0246 = 24.6 mW, and at 3 A it is 9 × 0.0246 = 221 mW.

Temperature rise for an external trace in free air follows empirically from the IPC-2221 curves rather than from a clean closed-form equation, because the actual heat transfer depends on trace orientation, nearby copper pours, solder mask coverage, and airflow conditions that no simple formula captures accurately. A direct calculation from first principles gives only an order-of-magnitude estimate that is useful for sanity checks but not for sign-off.

Using IPC-2221 rather than first-principles estimates

The IPC-2221 tables provide the accepted engineering values for layout sign-off. Internal layers run hotter than external layers at the same current because they lack direct air cooling, and IPC-2221 provides separate tables for each. When the operating ambient exceeds 25°C, subtract the ambient from the insulation temperature limit to find the true allowable temperature rise before looking up the trace width. For a board that operates at 60°C ambient with a maximum allowable temperature of 130°C, the available temperature rise is only 70°C instead of the 105°C assumed at 25°C ambient, and the required trace width increases by roughly 30 percent to compensate.

Reading IPC-2221 trace width tables

IPC-2221 Table 6-1 (external conductors) gives the minimum trace width for a given current and temperature rise above ambient.⁴ For 1-ounce copper, a 1 A trace with a 10°C temperature rise requires approximately 0.4 mm width. A 3 A trace at the same temperature rise needs approximately 1.4 mm. At 5 A the minimum width reaches approximately 2.7 mm.

For internal layers, where heat cannot dissipate directly to air and must instead conduct through dielectric layers with poor thermal conductivity, IPC-2221 requires significantly wider traces for the same current and temperature rise.⁴ A 3 A internal trace in 1-ounce copper with a 10°C rise needs approximately 2.6 mm, almost twice the external figure. Furthermore, the temperature rise budget should account for ambient operating temperature: a trace rated for 10°C rise at 25°C ambient may hit the FR4 glass-transition temperature at 125°C ambient with no margin. Always add the maximum expected ambient to the IPC-2221 temperature rise when evaluating trace sizing, because a board destined for an enclosed automotive ECU at 85°C ambient has far less thermal headroom than one sitting in a climate-controlled lab.

For 2-ounce copper, which is twice as thick as 1-ounce, sheet resistance drops to roughly 0.25 mΩ per square, which means every trace on that layer carries twice the current for the same width and temperature rise, or equivalently, you can halve the trace width and still meet the same thermal budget. Heavier copper lets you achieve the same current capacity in a narrower trace, which helps in dense layouts where routing space is limited. It also improves thermal spreading on power planes, reducing the temperature gradient between the trace and the surrounding copper pour, and the improved thermal conductivity helps move heat away from hot spots before they become reliability problems.

Using copper pours instead of traces for high-current paths

When the IPC-2221 table calls for a trace wider than practical for your layout, flood the area with a copper pour instead of routing a discrete trace. A copper pour on the top layer connected to the net with multiple vias distributes current across the entire filled area, reducing both resistance and temperature rise. For a 5 A path that would need a 2.7 mm trace, a 10 mm wide copper pour on 1-ounce copper provides roughly the same current capacity with better thermal performance because the surrounding copper acts as a heatsink. Connect the pour to the pad with a thermal relief or direct connect depending on whether you need solderability or maximum current capacity.

Via current capacity and why vias derate faster than traces

Vias are not free current highways. A via has barrel resistance determined by its drill diameter, plating thickness, and copper quality, all of which vary across production batches. Multiple vias in parallel reduce the net resistance, but plating variation and thermal stress make them far less predictable than a solid copper pour of equivalent cross-section. Treating a via as a perfect conductor is a common layout mistake that shows up only after prototypes overheat in the lab.

For high-current paths, use several vias in parallel rather than relying on a single via to carry the full current, connect them to large copper pours on adjacent layers to spread the current entry and exit points, and verify the manufacturer's finished hole plating capability before relying on via resistance estimates, because a via with thinner-than-specified plating can become a bottleneck that overheats while the surrounding traces remain cool.

Including vias in the I²R heating calculation

If a via carries current between layers, include it in the same I²R heating calculation as the traces it connects rather than assuming it contributes negligible resistance, because a single undersized via in a high-current path can become the weakest thermal link even when the copper traces on either side are generously sized and well within their thermal budget. A string of vias with inadequate plating can become the hottest point in a power path even when the traces on either side are properly sized.

A standard 0.3 mm drill via with 25 µm plating has a barrel resistance of roughly 10 to 15 mΩ. At 3 A, that is about 135 mW per via, which is manageable with proper thermal relief. measure a trace's I²R dissipation to confirm the pour width you need. But at 10 A, the same via dissipates over 1 W, and if the plating is thinner than specified or the barrel has voids, the localised heating can crack the via barrel over time. For currents above 5 A, use multiple vias in parallel or specify filled vias with copper paste to increase the effective conductor cross-section. Five such vias in parallel drop the combined resistance to roughly 1.5 mΩ, which is a common configuration for power distribution.

When to use this

Use this guide when reviewing a PCB layout before fabrication to confirm that power traces, motor driver output traces, and ground returns carry their rated current without unacceptable temperature rise. Reference it when estimating the resistance and voltage drop of a power distribution network across a large board.

Examples